Job DescriptionExperience: 4 to 12 Years.
nLocation: Bangalore.
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- n
- Must have hands-on experience coding in System Verilog/UVM.n
- Experience developing testbenches for block level or IP level verification.n
- Experience working on subsystem or SoC level would be helpful.n
- Candidates should be proactive in communication and be able to work independently to self-manage the deliverable as per the schedules.n
- Developing and maintaining block level test benches.n
- Vplan, regression and coverage closure.n
- Work on testbenches with real number modeling.n
- Netlist and Gate level simulations.n
nNotice Period: 30 to 90 days
📌 Sr./ Lead Design Verification (Vasanthanagar)
🏢 ACL Digital
📍 Vasanthanagar
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