Senior Silicon Design Engineer | STA | Synthesis (Vasanthanagar)

Senior Silicon Design Engineer | STA | Synthesis (Vasanthanagar)

12 Aug
|
smartsoc solutions
|
Vasanthanagar

12 Aug

smartsoc solutions

Vasanthanagar

Job DescriptionWe are seeking a highly skilled Senior Silicon Design Engineer with proven expertise in advanced technology nodes ( that directly influence product performance and customer success.
nKey Responsibilities:
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- n
- Timing Closure Leadership: Deliver sign-off quality STA across complex, high-frequency designs, ensuring robust performance in diverse modes and corners.n
- Customer Impact: Translate technical excellence into measurable outcomes for customers — faster turnaround, improved QoR, and optimized PPA trade-offs.n
- Constraint Development: Architect and validate timing constraints to guarantee design reliability and seamless integration into customer workflows.n
- Synthesis & Optimization: Own synthesis flows using Fusion Compiler and Design Compiler, achieving customer-defined targets for timing, area, and power.n
- Cross-functional Collaboration: Partner with RTL, PD, and DFT teams to proactively resolve design challenges, ensuring smooth delivery for customer programs.n
- AI-driven Design: Apply reinforcement learning tools (DSO.ai)



to accelerate design space exploration, delivering innovative solutions that reduce cycle time.n
- Low Power & UPF: Implement and verify UPF-based power intent, ensuring energy-efficient designs aligned with customer requirements.n
- Formal Equivalence & ECOs: Guarantee functional correctness through formal verification and ECO generation, enabling reliable customer tape-outs.n

nQualifications:
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- Bachelor's degree in Electrical Engineering from reputed universitiesn
- 7+ years of semiconductor design experience at leading companiesn
- Expertise in STA, synthesis, constraints, and low-power verification.n
- Proficiency in industry-standard tools: PrimeTime, Fusion Compiler, Design Compiler, Formality, ICC2, Conformal, VCLP.n
- Robust programming skills in TCL, Python, Perl, and Verilog.n
- Deep understanding of advanced node challenges (cross talk, OCV, AOCV, POCV) and clock architectures.n

📌 Senior Silicon Design Engineer | STA | Synthesis (Vasanthanagar)
🏢 smartsoc solutions
📍 Vasanthanagar

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