Job DescriptionLead RTL Design Engineer (ASIC)
nLocation: Chennai, Tamil Nadu
nExperience: 6 to 9 Years
nJob Description
n6 to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Positive knowledge of Power is preferable.
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- Strong Domain Knowledge on RTL Design, implementation, and Timing analysis.n
- Experience with RTL coding using Verilog/VHDL/System Verilog.n
- Experience in micro-architecture & designing cores and ASICs.n
- Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc.n
- Exposure in scripting (Pearl/Python/TCL).n
- Strong debugging capabilities at Synthesis, timing analysis & implementationn
- Collaborate closely with cross-function team to research, design and implement performance, constraints and power management strategy for product roadmap.n




- Good team player. Need to interact with the other teams/verification engineers proactively.n
- Ability to debug and solve issues independently.n

nAbout Company
nACL Digital, part of the ALTEN Group, is a trusted AI-led, Digital & Systems Engineering Partner driving innovation by designing and building intelligent systems across the full technology stack — from chip to cloud. By integrating AI and data-powered solutions, we help enterprises accelerate digital transformation, optimize operations, and achieve scalable business outcomes. Partner with us to turn complexity into clarity and shape the future of your organization.

📌 Lead RTL Design Engineer (Chennai)
🏢 ACL Digital
📍 Chennai