Job DescriptionJob Description:
nRole: Senior RTL Design Engineer
nExperience: 6 - 12 Years of Experience
nLocation: Bangalore/ Hyderabad
nWork Mode: Work from office
nRequired Skills
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- Experience in Logic design / RTL coding is a must.n
- Experience is SoC design and integration for complex SoCs is a must.n
- Experience in Verilog/System-Verilog is a must.n
- Experience in Multi Clock designs, Asynchronous interface is a must.n
- Experience in using the tools in ASIC development such as Lint and CDC.n
- Experience in Synthesis / Understanding of timing concepts is a plus.n
- Experience in ECO fixes and formal verification.n
- Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture.n
- Excellent oral and written communications skills.n
- Proactive, creative, curious, motivated to learn and contribute with positive collaboration skillsn