RTL Design Engineer (Vasanthanagar)

RTL Design Engineer (Vasanthanagar)

12 Aug
|
ACL Digital
|
Vasanthanagar

12 Aug

ACL Digital

Vasanthanagar

Job DescriptionJob Title: RTL Design Engineers
nExp Level: 5+ yrs
nLoctaion: Hyderabad/Bangalore
nJob Description:
n• RTL coding knowledge
n• Top-level (SOC) level basic industry standard Arch knowledge
n• SoC & IP level Integration knowledge
n• IPXACT knowledge
n• IORING and Phys & GPIOs basic functionality
n• Design Partitioning(Tilification) knowledge
n• Design RTL quality checks:
n
- n
- Clock domain crossing(CDC)n
- Reset domain crossing(RDC)n
- LINTn
- VSIn
- UPF knowledgen
- LEC(Logic equivalence check)n
- Timing concepts & SDC knowledgen

n• Tools knowledge:
n
- n
- Vc_static or equivalent other tools(VSI)n
- VC_spyglass LINT, CDC and RDCn
- 0inn
- Formality and conformal LEC tooln

n• Design and scripting languages:
n
- n
- Verilog and SVn
- Perln
- Pythonn
- TCLn

📌 RTL Design Engineer (Vasanthanagar)
🏢 ACL Digital
📍 Vasanthanagar

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