Job DescriptionWe are seeking an experienced, highly motivated and high-caliber individual with below expertise. Does this sound like a good role for you?
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- Staff RTL Design Engineer (R&D; Engineeringn
- )Location: Bangalorn
- eExperience: 7yrs to 15yrn
- sBSEE/MSEE in Electrical Engineering, Computer Engineering, or a related fieldn
- .7 years of hands-on experience in RTL design and verificationn
- .Proficiency in Verilog, RTL Coding, Spyglass, industry-standard quality tools (Lint, CDC, RDC, Synthesis) ,TCL scripting, and Formal Verification methodologiesn
- .Knowledge of DFT, digital, analog, and mixed-signal IP/circuit design (a plus)n
- .Experience working in Unix/Linux environmentsn
- .Strong debugging and problem-solving skills, especially in complex chip design environmentsn
- .Familiarity with 3D-IC standards and semiconductor verification best practices (desirable)n
- .Responsibilitiesn
- :Designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projectsn




- .Developing comprehensive test cases to ensure robust product functionality and performancen
- .Collaborating with customers and internal engineering teams to resolve technical issues, including hands-on debugging and root cause analysisn
- .Staying current with emerging trends, standards, and best practices in SLM and 3D-IC technologiesn
- .Contributing to the improvement of verification methodologies and automation flowsn
- .Documenting design specifications, verification plans, and results to ensure transparency and repeatabilityn
- .Participating in code reviews and technical discussions to drive innovation and continuous improvementn

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- y. Inclusion and Diversity are key to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, a

📌 Senior Staff RTL Design Engineers (Vasanthanagar)
🏢 Synopsys
📍 Vasanthanagar