Category EngineeringHire Type EmployeeJob ID 12395Remote Eligible NoDate Posted 04 08 2025 Job Title ASIC Verification- Sr Engineer We Are At Synopsys we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence from self-driving cars to learning machines We lead in chip design verification and IP integration empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation You Are You are an accomplished verification engineer with a passion for excellence and a track record of delivering robust high-quality IP solutions You thrive in a fast-paced dynamic environment and are excited by the opportunity to work on next-generation connectivity protocols that power commercial enterprise and automotive applications With a solid foundation in Electrical Electronics Engineering BSEE with 2 years or MSEE with 2 years of relevant experience you bring deep expertise in System Verilog and industry-standard verification methodologies such as UVM OVM VMM Your hands-on experience developing HVL-based test environments and extracting meaningful verification metrics sets you apart as a technical leader You are a collaborative team player who values knowledge sharing and actively contributes to a culture of continuous improvement Your familiarity with protocols like MIPI-I3C UFS AMBA Ethernet DDR PCIe and USB allows you to quickly ramp up on new projects and deliver results You bring a strong analytical mindset exceptional debugging skills and a drive to meet and exceed quality metrics Experienced with scripting languages like Perl TCL and Python you automate processes for efficiency and scalability Your solid communication skills initiative and global perspective enable you to work effectively with cross-functional and multi-site teams Above all you are a lifelong learner who embraces challenges adapts to new technologies and is committed to shaping the future of silicon design What You ll Be Doing Specify architect and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies Develop and execute comprehensive test plans ensuring coverage of unit-level and system-level requirements Design code and debug testbenches test cases and functional coverage models to validate complex IP functionalities Perform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics Collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure Leverage scripting Perl TCL Python to automate verification flows streamline processes and enhance productivity Contribute to the development and refinement of verification methodologies including VIP development and formal verification approaches The Impact You Will Have Ensure the delivery of high-quality robust IP cores that power critical applications in commercial enterprise and automotive markets Drive innovation in verification methodologies setting new standards for efficiency and coverage Enhance time-to-market by identifying and resolving design and verification issues early in the development cycle Strengthen Synopsys reputation as a leader in silicon IP and verification through technical excellence and customer focus Mentor and support junior engineers fostering a culture of learning and continuous improvement Contribute to the success of global multi-site R D teams by providing expertise and driving cross-functional collaboration What You ll Need BSEE with 2 years or MSEE with 2 years of relevant experience in ASIC or IP verification Expertise in developing HVL System Verilog -based verification environments and testbenches Strong hands-on experience with industry-standard simulators VCS NC MTI and debugging tools Proficiency in verification methodologies such as UVM OVM or VMM exposure to formal verification is highly desirable Solid understanding of protocols such as MIPI-I3C UFS Unipro AMBA SD eMMC Ethernet DDR PCIe USB Familiarity with scripting languages Perl TCL Python and HDLs Verilog experience with VIP development is a plus Demonstrated ability to work with functional coverage-driven methodologies and quality metric goals Who You Are Analytical thinker with strong problem-solving and debugging skills Excellent verbal and written communication abilities Team player who thrives in collaborative multi-site environments Proactive self-motivated and able to take initiative on challenging projects Detail-oriented quality-focused and driven by a desire to excel Adaptable and eager to continuously learn andnew technologies The Team You ll Be A Part Of You will join the Solutions Group s DesignWare IP Verification R D team a highly skilled and diverse group of engineers dedicated to delivering world-class IP cores for next-generation connectivity The team operates in a collaborative multi-site environment leveraging global expertise to solve complex verification challenges Together you will drive innovation