12 Aug
|
LT-Larsen & Toubro
|
Bengaluru
12 Aug
LT-Larsen & Toubro
Bengaluru
Purpose:
LTSCT’s Chief Development Organization and Global Engineering team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for LTSCT's Automotive, Industrial, Energy and Telecom infra business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low power devices to highly integrated, high performance, multi-domain devices compliant with the latest automotive and industrial safety and security standards.
Areas of Responsibilities:
- Contribute to the RTL delivery for a multitude of projects.
- Work closely with system architects to define high level specifications that are implementable and robust, and Interface with verification/validation teams to ensure design quality and robustness.
- Build solid collaboration with other R&D; teams such as Verification, digital IP, Design Enablement, Emulation, and Validation to achieve project milestones.
- Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips.
- Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence.
Qualifications:
- At least 4+years of experience in related domains and have working knowledge.
- Degree in Electrical Engineering or Computer Science, with 7+ years of experience on IP/Sub-System RTL Design.
- Experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.
- Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency.
- Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers.
- Experience and knowledge of Verilog, System Verilog, C/C++, Shell.
- Good knowledge in scripting like Perl, TCL or Python is a plus.
- Proficiency in Metric Driven Verification concepts, functional and code coverage.
- Expertise in directed and constrained random m
📌 Senior RTL Design Engineer (Bengaluru)
🏢 LT-Larsen & Toubro
📍 Bengaluru