Lead RTL Design Engineer (Hyderabad)

Lead RTL Design Engineer (Hyderabad)

12 Aug
|
Silicon Labs
|
Hyderabad

12 Aug

Silicon Labs

Hyderabad

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for cutting-edge solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.
Role Overview
The RTL Design Engineer for Mixed-Signal IPs is responsible for developing, integrating, and verifying digital RTL blocks within mixed-signal subsystems that combine analog and digital functionalities. This role requires a deep understanding of digital design principles, interface with analog/mixed-signal teams, and strong verification and integration skills to ensure high-quality, low-power, and functionally robust IP delivery. The engineer will work closely with system architects,



analog designers, and SoC teams to enable seamless integration of mixed-signal IPs into complex SoCs.
Key Responsibilities
- Develop synthesizable, high-quality RTL for mixed-signal IPs such as ADC/DAC interfaces, PLL/DLL control, power management units, and sensor front-ends.
- Collaborate with analog design engineers to define digital-analog interface specifications, control logic, and communication protocols.
- Ensure correct functionality and performance of mixed-signal IPs through behavioral modeling, simulation, and co-verification with analog components.
- Participate in design reviews, micro-architecture definition, and documentation of IP functionality and timing interfaces.
- Perform design quality checks including lint, CDC, RDC, and synthesis readiness analyses.
- Collaborate with verification engineers to define test plans, drive coverage closure, and debug issues across digita

📌 Lead RTL Design Engineer (Hyderabad)
🏢 Silicon Labs
📍 Hyderabad

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