- Industry experience in analog/mixed signal behavioral modeling at various levels of abstraction and full chip verification (AMS and DMS DV) using SV RNM or Custom UDNs.
- Valuable understanding of analog design concepts and mixed signal design architectures. Exposure to products that integrate a wide variety of Analog/Mixed-Signal building blocks such as Power Management, PLL/Synthesizers, bandgap references, oscillators, SerDes etc. and related digital control and signal processing.
- Demonstrated experience of verification plan development, UVM verification environment development/debug and verification of complex mixed signal products at block, Subsystem & chip-top levels.
- Familiarity with Analog/Mixed-Signal/RF design architectures and debug experience with schematic capture tools such as Cadence Virtuoso and waveform viewers such as Cadence Simvision.
- Experience of co-simulations with analog model/transistor level and digital RTL/Gate+SDFs,
experience of circuit simulations with Spice/Fast Spice simulators.
- Experience and debug with digital simulators such as Cadence Xcelium/DMSO/Synopsys VCS.
- Experience in developing self-checking testcases, functional/code coverage & formal verification.
- Tracking of verification metrics and regression management, Metric Driven Verification (MDV) framework using tools such as Cadence vManager.
- Experience in closing the verification of analog designs using industry standard metrics is a must.
- Quick to adopt new technologies with good problem-solving skills.
- Collaborate and work closely with team members from various disciplines (system architects, digital design, analog design, digital DV etc.).
- Self-motivated and enthusiastic.