Physical design engineer – asic/soc (Ernakulam)

Physical design engineer – asic/soc (Ernakulam)

12 Aug
|
HCLTech
|
Ernakulam

12 Aug

HCLTech

Ernakulam

HCLTech is a leading global technology company, recognized for delivering cutting-edge digital, engineering, and cloud solutions to enterprises worldwide. With a solid presence in over 50 countries and a workforce of more than 220,000 professionals, HCLTech has consistently been at the forefront of innovation, leveraging its deep domain expertise and robust R&D; capabilities. The organization is committed to driving customer success through a culture of collaboration, integrity, and continuous learning, and has been repeatedly acknowledged among the top employers and most innovative technology providers globally.
Overview of the Role
As a Physical Design Engineer at HCLTech, you will play a pivotal role in the end-to-end implementation of advanced ASIC/So C designs. You will be responsible for delivering high-quality, power-optimized, and timing-closed layouts for state-of-the-art semiconductor products, working closely with cross-functional teams to ensure first-time-right silicon.



This role offers an opportunity to contribute to high-impact projects that drive the next generation of technological advancements in the semiconductor industry.
Detailed Responsibilities:
Execute and optimize floorplanning, power planning, placement, clock tree synthesis (CTS), and routing for complex ASIC/So C designs.
Perform physical verification tasks including layout versus schematic (LVS), design rule check (DRC), and electrical rule check (ERC) using industry-standard tools such as Calibre.
Implement and manage Engineering Change Orders (ECOs) and ensure efficient design modifications.
Drive timing closure efforts, including multi-corner multi-mode (MCMM) analysis, using tools such as Prime Time and Tempus.
Conduct Static Timing Analysis (STA), setup/hold analysis, signal integrity (SI) analysis, crosstalk analysis, and manage on-chip variation (OCV, AOCV, POCV).
Develop and validate Synopsys Design Constraints (SDC) and TCL scripts for automation and verification.
Perform IR dro

📌 Physical design engineer – asic/soc (Ernakulam)
🏢 HCLTech
📍 Ernakulam

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