Location- Bangalore/ Noida/ Hyderabad
4+ years experience in STA/Synthesis
Hand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.
Synthesis Quality with FE Inputs, LEC setting, UPF Cleanup, Generic Partition level UPF ? and VCLP Signoff.
USER mode SDC (will have generic dft constraints), Generic DFT SDC, GCA, Flat Timing convergence, Timing Signoff, Merging Modes
Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.
Knowledge on the Timing closure on Sub system level & Block level and Chip level.
Knowledge on Writing Manual ECO’s to fix timing violations and DRC’s.
Knowledge on constraint development.
Good Knowledge of TCL scripting and UNIX env.
Leading the team 4 to 5 team members by guiding and mentoring on the STA /Synthesis.
Prelayout timing analysis and report out Post layout timing analysis for placement, CTS & PRO Clock gating checks and timing closure ECOs and final tapaout timing closure skills across corners and modes Must work RTL design team, PD team and HMs team for overall timing closure for SoC