Company Description
LeadIC Design Pvt Ltd is a semiconductor engineering services company providing end-to-end VLSI solutions across digital, analog, memory, verification, physical design, and FPGA prototyping. With engineering teams across India and Canada, LeadIC partners with global semiconductor companies to deliver high-quality design and implementation solutions.
Role Description
The Senior Physical Design Engineer will be responsible for end-to-end ASIC physical design activities from synthesis through place-and-route, timing closure, and physical signoff. The role requires hands-on experience with advanced-node technologies, strong physical design expertise, and the ability to work independently on complex implementation challenges.
Qualifications
Strong experience in ASIC Physical Design and RTL-to-GDSII implementation.
Hands-on experience with TSMC lower/advanced nodes – Mandatory.
Hands-on experience with Innovos – Mandatory.
Strong knowledge of synthesis, floorplanning, placement,



CTS, routing, optimization, and timing closure.
Experience with STA, power analysis, IR drop, EM, DRC, LVS, and signoff.
Experience with industry-standard EDA tools such as Synopsys, Cadence, or Siemens.
Good understanding of advanced-node physical design challenges, including timing, congestion, power, and PPA optimization.
Strong debugging and problem-solving skills.
Good communication and collaboration skills.
Screening Criteria
Must Have:
TSMC lower/advanced-node experience
Innovos tool experience
Strong hands-on Physical Design experience
Candidates who do not have both TSMC lower-node and Novos experience may not be considered for this position.
Location: Bengaluru
Work Mode: Hybrid
Employment Type: Full time
Interested candidates can reach out to:
nagu.ms@leadicdesign

📌 Senior Physical Design Engineer (Bengaluru)
🏢 leadIC Design
📍 Bengaluru