Senior FPGA Prototyping Engineer | 6+ Years | Bangalore
Location: Bangalore
Experience: 6+ Years
Role: Senior FPGA Prototyping Engineer
Job Summary
We are looking for an experienced FPGA Prototyping Engineer with 6+ years of hands-on experience in FPGA-based ASIC/SoC prototyping, RTL integration, FPGA implementation, debug and validation. The candidate should have robust knowledge of FPGA architecture, synthesis, timing closure, high-speed interfaces and hardware/software co-verification.
Key Responsibilities
Develop and maintain FPGA prototypes for complex ASIC/SoC designs.
Perform RTL integration, FPGA synthesis, implementation and bitstream generation.
Port large ASIC designs to FPGA prototyping platforms.
Analyze and resolve FPGA synthesis, implementation and timing issues.
Perform RTL modifications required for FPGA prototyping while maintaining ASIC functionality.
Develop FPGA constraints including XDC/SDC, clock constraints, I/O constraints and timing exceptions.
Perform timing analysis and timing closure on FPGA designs.
Debug RTL and FPGA hardware issues using simulation and on-board debug.
Use ILA/ChipScope/SignalTap for hardware debug and signal visibility.
Develop and execute FPGA bring-up and validation plans.
Support hardware/software co-verification and system-level validation.
Integrate processors, memories and peripheral IPs into FPGA prototypes.
Debug communication and high-speed interfaces.
Work with firmware/software teams to enable early software development on FPGA prototypes.
Automate FPGA build, regression and validation flows using scripting.
Collaborate with RTL, verification, ASIC, firmware, software and system teams.
FPGA Skills
Strong hands-on experience with one or more:
AMD/Xilinx FPGA
Vivado
Vitis
ILA
ChipScope
Zynq / Versal
Intel/Altera FPGA
Quartus
SignalTap
Platform Designer
FPGA synthesis and implementation.
FPGA floorplanning and resource optimization.
LUT, FF, BRAM, URAM and DSP utilization analysis.
Clocking resources, PLL/M