Description
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Experience: 3+ yrs
Location: Bengaluru
Job Type: Full time

We are looking for a skilled Memory Layout Engineer with hands-on experience in advanced semiconductor technology nodes to design and optimize high-performance memory layouts. This role is ideal for professionals with expertise in Memory Layout, TSMC 2nm & TSMC 3nm technologies, DRC, and LVS, along with a strong understanding of physical design methodologies and layout optimization.
As a Memory Layout Engineer, you will be responsible for developing accurate and manufacturable memory layouts while ensuring compliance with foundry design rules and quality standards. You will collaborate closely with circuit designers, physical design engineers, verification teams, and process engineers to deliver optimized memory macros that meet performance, power, and area (PPA) targets.



This role offers the opportunity to work on cutting-edge process technologies and contribute to the development of next-generation semiconductor products.

Requirements
Key Responsibilities
- Design and develop high-quality memory layouts for advanced technology nodes, including TSMC 2nm and TSMC 3nm.
- Create optimized layouts for SRAM and other memory blocks while meeting performance, power, and area objectives.
- Perform layout verification using Design Rule Check (DRC), Layout Versus Schematic (LVS), and other physical verification tools.
- Identify and resolve layout-related issues, ensuring compliance with foundry design rules and manufacturing requirements.
- Collaborate with circuit design, physical design, and process teams to achieve optimal layout quality and functionality.
- Optimize layouts for signal integrity, reliability, electromigration, and manufacturability.
- Participate in layout reviews and implement feedback to improve design quality and efficiency.
- Support tape-out activities by ensuring layouts are v

📌 Memory Layout (Bengaluru)
🏢 Weekday AI
📍 Bengaluru