Key Responsibilities:
- Work with system architect to understand the requirements and design effective RTL implementations targeting FPGAs.
- Translate MATLAB models to RTL for hardware realization
- MATLAB/Simulink based modelling, simulation and conversion to RTL
- Develop RTL architecture and microarchitecture based on algorithm requirements
- Implement RTL (Verilog/VHDL/SystemVerilog) for blocks like ORAN, ORAN IP compression, Digital filters, FFT engines, time synchronization protocols, JESD 2.5
- Perform functional verification, linting, and synthesis of RTL designs
- Implement on FPGA systems and validate the performance
- Collaborate with verification, and firmware teams to ensure end-to-end integration and functionality
- Support bring-up and on board validation as required
Required Skills & Experience:
- Strong RTL design skills in VHDL with knowledge of digital signal processing fundamentals
- Familiarity with verification methodologies desirable (UVM/SystemVerilog preferred)
- Exposure to FPGA design flow including synthesis, implementation, STA and timing closure
- Exposure in AMD and Altera tool flows – hands on experience on Altera Agilex FPGA or AMD(Xilinx) Zynq RFSoC highly desired
- Good debugging skills and ability to analyze RTL and simulation mismatches
- Preference 1:
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- Proficient in MATLAB/Simulink for algorithm modeling, fixed-point conversion, and simulation
- Solid understanding of ORAN domain – control and data planes
- Experience in lower and upper layer protocol implementation in wireless domain
- Experience in wireless stack packet processing – Layer 2/Layer 3 switching etc.
- Preference 2: If not wireless domain exposure, experience in wireline Ethernet packet processing capabilities can also be considered with complexity level of routing or switching function implementation
- Preference 3: If not wireless or wireliene packet processing domain exposure, Experien
📌 RTL Design Engineer (Bengaluru)
🏢 Right Advisors
📍 Bengaluru
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