Role description:
Key ResponsibilitiesExecute floorplanning, placement, CTS, routing, and timing closure.
Drive power, performance, and area (PPA) optimization.
Conduct physical verification (DRC/LVS) and sign-off checks.Work on multi-voltage, low-power design techniques and UPF/CPF flows.
Support ECO implementation and tape-out activities.
Required Skills & Qualifications
3-5 years of experience in ASIC/SoC physical design.
Robust knowledge of EDA tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, PrimeTime, Voltus, etc.).
Expertise in timing analysis, signal integrity, and power analysis.
Experience with advanced nodes (e.g., 16nm, 5nm).
Familiarity with DFT insertion, low-power design, and multi-clock domain handling.
Good understanding of physical verification and manufacturing sign-off.
Strong problem-solving and debugging skills.
Experience in working on Automotive or Industrial MPU/MCU SoCs (preferred for safety-critical designs and compliance with standards like ISO 26262).
Preferred Qualifications




Experience with high-performance SoCs or complex IP blocks.
Knowledge of EM/IR analysis and reliability checks.
- Familiarity with scripting languages (Tcl, Perl, Python) for flow automation.
Education
Bachelor s or Master s degree in Electrical Engineering, Electronics, or related field.

Skills

vlsi design,physical design,low power design,floor planning,electrical engineering
About UST

UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.

📌 Associate Ii (Bengaluru)
🏢 UST
📍 Bengaluru