Summary
The Lead PERC Rule Developer will drive PERC methodology, rule development, and flow enablement for ESD, latch-up, power-domain, connectivity, and reliability-related verification. The role requires strong hands-on expertise in Calibre LVS/PERC, CMOS and FinFET fundamentals, analog/mixed-signal design flows, and close collaboration with cross-functional design, CAD, technology, and verification teams across multiple sites and time zones.
Job Qualification
BTech/BE/ME/MTech in Electronics & Communication, Electrical Engineering, Microelectronics, VLSI, or a related discipline with at least 10 years of relevant industry experience.
Strong hands-on expertise in PERC (Programmable Electrical Rule Check) rule development, debugging, validation, and deployment in production design environments.
Good understanding of ESD fundamentals, including HBM, CDM, and system-level ESD models, along with modern ESD protection techniques and verification methodologies.
Proficiency in scripting and programming languages such as TCL, Perl, Python, SKILL, and TVF/SVRF for rule automation,



flow development, debug utilities, and regression infrastructure.
Good understanding of analog and analog mixed-signal design flows, including schematic, layout, extraction, simulation, and signoff dependencies.
Solid understanding of CMOS fundamentals, including advanced-node and FinFET technologies, device behavior, layout effects, and reliability considerations.
Experience with EDA tools such as Cadence Virtuoso, Siemens Calibre PERC/LVS. Knowledge of Cadence Quantus or equivalent extraction and verification platforms is a plus.
Experience in leading physical verification flows across IP, block, subsystem, and SoC levels throughout different stages of the design cycle.
Familiarity with AMS verification and transistor-level RC extraction is an advantage.
Experience working with cross-functional design, CAD, technology, foundry/interface, and product teams across different time zones.
Solid in

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