Job Details:
Job Description:
We are seeking a highly experienced Director, STA & PD Closure to lead timing closure and physical design closure efforts across complex, advanced-node SoC programs. The ideal candidate brings approximately 20 years of hands-on and leadership experience in the semiconductor industry, with a strong track record of driving multiple designs through STA closure and tapeout. This is a senior technical leadership role requiring deep expertise in timing closure methodologies, cross-functional collaboration, and ownership of sign-off quality from RTL freeze through tapeout.
Key Responsibilities
Own and drive end-to-end STA (Static Timing Analysis) and Physical Design (PD) closure for complex SoC/ASIC designs at advanced technology nodes.
Lead timing closure strategy across multiple blocks/chips, including setup/hold analysis, clock domain crossing, multi-corner multi-mode (MCMM) sign-off, and margining.
Drive full-chip tapeout readiness, ensuring timing, physical, and sign-off criteria are met within schedule.
Partner closely with RTL, synthesis,



place-and-route, and physical verification teams to resolve timing and physical closure bottlenecks.
Define and continuously improve STA and PD closure methodologies, flows, and best practices across projects.
Debug and resolve complex timing violations, including crosstalk, variation-aware timing, and advanced-node signoff challenges.
Mentor and build a strong team of STA/PD engineers; provide technical leadership and career guidance.
Interface with foundry/IP partners and internal stakeholders on timing and closure-related sign-off requirements.
Report closure status, risks, and mitigation plans to senior engineering and program leadership.
Drive root-cause analysis and process improvements to reduce closure cycle time across projects.
Qualifications:
Approximately 20 years of relevant industry experience in semiconductor design, with a robust focus on STA and Physical Design closure.
Deep, hands-on

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