Requirements: -B.Tech / M.Tech (preferred) with 5-15 years of experience in DFT
Solid knowledge of DFT architecture, methodologies and structural debug concepts
-Experience in JTAG,Mbist, Scan tests debug
-Experience in handling DFT of the large multi multimillion gate multi clock domain SoCs
-Hands on experience in SCAN, ATPG and JTAG implementation at block and chip level
-Knowledge of Verilog RTL and hands on experience in using simulators and waveform
-debugging tools such as VCS and Verdi -Hands on experience in using Synopsys DFT tools like Testmax, Tetramax, DC & FC
-Experience in post silicon debug -Knowledge of Python, , Shell scripting, Makefiles, TCL
-Excellent problem solving skills and highly self-motivated.