Job Description Below is the JD for RTL engineers. We need to build solid RTL team.
/n /n Minimum 8+ years of work experience in ASIC RTL Design, Synthesis, STA & FV
/n Experience in Logic design/micro-architecture/RTL coding is a must.
/n Must have hands on experience with design and integration of complex multi clock domain blocks
/n Experience in Verilog/System-Verilog is a must.
/n Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architecture
/n Hands on experience in Multi Clock designs, Asynchronous interface is a must.
/n Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.
/n Work closely with the Design verification and validation teams for pre/post Silicon debug
/n Hands on experience in Low power design is preferable
/n Experience in Synthesis / Understanding of timing concepts for ASIC is must
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