At AMD, our mission is to build outstanding products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
Responsibilities:
SMTS SILICON DESIGN ENGINEER
- Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC (Mostly Working on Calibre tool)
- Experience in IO, Bump planning and fullchip RDL generation for Power & IO/Signals
- Work on physical verification (DRC/LVS) of state-of-the-art SOCs/digital IPs/blocks at cutting edge technology nodes of various foundries.
- Work hands-on to solve critical design and execution issues related to physical verification and sign-off
- Strong Technical problem and debugging solving.
- Own physical verification and sign-off flows, methodologies and execution of SoCs
LI-PK2
Qualifications:
- Benefits offered are described: _AMD benefits at a glance.-
- AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available _here._- This posting is for an existing vacancy._