Analog / Mixed-Signal Design Engineer
Device & Variability Characterization
Team: Crypto / Security IP Reports to: PUF Architect
Level: Junior (03 years post-degree, or solid new-grad with relevant internship/research experience)
About the Role
We are developing critical transistor characteristic dependant circuits for our crypto subsystem, currently being ported from GF 22FDX to TSMC 12FFC. This requires SPICE-level work to validate that the digital architecture's entropy and reliability assumptions actually hold on real silicon.
You'll work directly with the PUF designer, translating architectural requirements into concrete circuit-level simulation, and feeding real numbers back into the architecture (frequency estimates, counter sizing, error budgets, weak-bit thresholds).
What You'll Do
- Set up and run Monte Carlo mismatch simulations (Synopsys HSPICE / PrimeSim) on circuit structures, separating local (mismatch) from global (process corner) variation sources.
- Build and maintain SPICE testbenches for standard-cell-based circuits at the transistor level,
matching RTL/gate-level structures exactly.
- Characterize device- and cell-level variability (RDF, LER, work-function variation) on TSMC 12FFC and translate results into entropy, uniqueness, and bit-error-rate estimates the digital architecture depends on.
- Support layout-level matching strategy (common-centroid, interdigitation, dummy device placement) for circuits where mismatch is the intended signal.
- Bring up and validate PDK statistical/MC model decks with the foundry confirm global/local variation separation is modeled correctly before results are trusted downstream.
- Help design and execute silicon characterization/validation plans (PVT sweeps, corner analysis) once test chips are available.
- Document simulation methodology and results clearly enough that a primarily-digital architect can act on them without needing to be an analog expert themselves.