We are looking for a skilled and motivated
STA Engineer
to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting performance, power, and area (PPA) optimization and signoff closure.
Key Responsibilities:
1. STA Engineer with 4+ years
- Timing closure fundamentals
- Constraint creation and maintenance exposure
- DFT modes in STA timing closure