Machine Learning Engineer (Bengaluru)

Machine Learning Engineer (Bengaluru)

13 Aug
|
Ixana
|
Bengaluru

13 Aug

Ixana

Bengaluru

What Youll Do

Build predictive models for PPA Timing:

Develop ML models to predict Power, Performance, Area, and timing violations critical paths, setup/hold slack at early RTL and synthesis stages to reduce costly signoff iterations.

Automate Physical Design:

Apply Reinforcement Learning RL and Graph Neural Networks GNNs to automate and optimize placement, routing, and floorplanning.

Process Chip Data at Scale:

Work directly with circuit netlist formats Verilog gate-level, LEF/DEF, SPEF, SDC, Liberty to build graph-based representations for ML consumption.

Deploy Closed-Loop ML:

Integrate trained ML models as closed-loop plugins within industry EDA tool scripts e.g., Tcl plugins so your predictions actively drive and influence real-time design decisions.

Predict Manufacturability:

Build DRC hotspot prediction models to catch lithography and design rule violations pre-tapeout.

Build Data Pipelines:

Architect pipelines to extract, label, and learn from massive simulation outputs generated by standard VLSI synthesis and physical design tools.





Collaborate Cross-Functionally:

Partner with RTL, physical design, and mixed-signal verification teams to identify bottlenecks and deploy your AI-assisted tooling into production flows.

What Were Looking For

Required:
- 3-6 years of ML/AI engineering experience or exceptional academic background/Masters/PhD focused on ML for EDA .
- Bachelors or Masters degree in Computer Science, Electrical Engineering, or a related field with a GPA of 9+ from IITs, NITs, BITS, or IISc.
- Deep ML/AI Expertise: Solid proficiency in Python and deep learning frameworks PyTorch or TensorFlow , specifically with experience in graph-based ML GNNs, graph transformers on structured relational data.
- Domain Knowledge STA Physical Design : Solid understanding of Static Timing Analysis STA concepts-timing paths, slack margins, clock trees, and signoff criteria-as well as the broader ASIC/SoC RTL-to-GDSII flow.
- EDA Data Fluency: Proven a

📌 Machine Learning Engineer (Bengaluru)
🏢 Ixana
📍 Bengaluru

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