- SOC Verification plan definition, DV environment development in SV/UVM
- Design verification at RTL/Gate level, DV Coverage analysis, Coverage improvement at block and Chip level
- Support of assertion and coverage-driven methodology
- Develop test cases to verify functional operation of that the system level
- Experience in PCIe or NVMe or UFS or DDR protocols
- Communicate test progress, test results, and other relevant information to project lead
- Test any recent software to ensure integration into company system meets functional requirements, system compliance, and technical specifications
- Analyze formal test results in order to discover and report any defects, bugs, errors, configuration issues, and interoperability flaws
- Code and functional coverage objects of different blocks
Disclaimer: This job description has been sourced from a public domain and may have been modified by Naukri.com to improve clarity for our users. We encourage job seekers to verify all details directly with the employer via their official channels before applying.