Role description

1–4 years of experience in ASIC/SoC Functional Verification. Solid proficiency in SystemVerilog and UVM. Good understanding of digital design fundamentals and verification methodologies. Experience with Verilog/SystemVerilog simulation and debugging. Knowledge of constrained-random verification and functional coverage. Familiarity with scripting languages such as Python, Perl, or Shell is an added advantage. Good debugging, analytical, and problem-solving skills. Excellent communication and teamwork skills. Preferred Qualifications Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field. Exposure to industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens QuestaSim. Knowledge of standard bus protocols such as AXI, AHB, APB, PCIe, USB, I2C, SPI, or UART is preferred.





Skills

SystemVerilog, PCIe, UVM, Verilog, AHB, APB, AXI

About UST
UST is a global digital transformation solutions provider. For more than 20 years, UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered by technology, inspired by people and led by purpose, UST partners with their clients from design to operation. With deep domain expertise and a future-proof philosophy, UST embeds innovation and agility into their clients’ organizations. With over 30,000 employees in 30 countries, UST builds for boundless impact—touching billions of lives in the process.

📌 Associate II (Bengaluru)
🏢 UST
📍 Bengaluru