ASIC/SOC Physical Design Engineer- Full Chip Floor Planning (Bengaluru)

ASIC/SOC Physical Design Engineer- Full Chip Floor Planning (Bengaluru)

13 Aug
|
Allegis Group
|
Bengaluru

13 Aug

Allegis Group

Bengaluru

We are Hiring Physical Design (PD) Engineer

Location: Bangalore, India
Experience: 5+ Years

We are looking for an experienced ASIC/SoC Physical Design Engineer with strong expertise in Full-Chip Floor planning and physical implementation.

Key Requirements:
5+ years of experience in ASIC/SoC Physical Design
Robust hands-on experience in Full-Chip Floor planning

Proficiency with industry-leading EDA tools:

ICC2,Fusion Compiler or Innovus

Strong understanding of:
Hierarchical integration
Pin planning
Routing architecture
Physical design methodologies
Scripting knowledge (Tcl/Perl/Python/Shell) is a plus

Preferred Skills:
Experience in advanced technology nodes
Timing, power, and congestion-aware floorplanning
Strong debugging and problem-solving skills

📌 ASIC/SOC Physical Design Engineer- Full Chip Floor Planning (Bengaluru)
🏢 Allegis Group
📍 Bengaluru

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