Senior Design And Verification Engineer (Bengaluru)

Senior Design And Verification Engineer (Bengaluru)

13 Aug
|
Pqangels Technologies
|
Bengaluru

13 Aug

Pqangels Technologies

Bengaluru

ABOUT PQANGELS

PQAngels is a product engineering company built for the silicon-to-software stack. Founded by engineers, we help customers accelerate innovation through Semiconductor, ASIC, VLSI, Embedded and Product Engineering services.

ROLE SUMMARY

We are seeking an experienced Design Verification Engineer with robust UVM expertise for SoC/IP verification. This role also requires proven experience in leading and mentoring a small team, with the ability to guide junior engineers through planning, execution, and signoff.

OUR REQUIREMENTS & EXPECTATIONS
- Experience: 5 to 10 years of hands-on experience in Design and Verification Engineering (SoC/IP level).
- Team Leadership: Demonstrated ability to lead, mentor, and manage a team of 3-4 verification engineers, including task allocation, progress tracking, and technical guidance.
- Ownership: Ability to independently own verification deliverables end-to-end and be accountable for the team's output and quality of signoff.
- Stakeholder Interface: Act as the primary technical point of contact for customer discussions related to project scope,



status, and issue resolution.

KEY RESPONSIBILITIES
- Develop verification plans.
- Build reusable UVM environments.
- Functional coverage closure.
- Assertions and debugging.
- Regression execution.
- Testbench development.
- Root cause analysis.
- Protocol verification.
- Customer interactions.
- Documentation.
- Verification signoff activities.
- Collaborate with RTL and PD teams.
- Lead and mentor a team of 3-4 design verification engineers, reviewing their work, unblocking technical issues, and ensuring on-time delivery.
- Plan and distribute verification tasks across the team in line with project milestones.
- Report team progress, risks, and coverage status to internal and customer stakeholders.

MANDATORY TECHNICAL SKILLS
- SystemVerilog
- UVM
- SVA
- Functional Coverage
- Python / TCL

Protocol Verification: AMBA, AXI, APB, AHB, PCIe, DDR, USB, Ethernet

EDA TOOLS
- V

📌 Senior Design And Verification Engineer (Bengaluru)
🏢 Pqangels Technologies
📍 Bengaluru

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