Your Job
- Work closely with the IP desig n teams and EDA vendors to develop methodologies and flows for front end design view generation and verification. Front-end design views include Verilog views enabling efficient RTL and RTL2GDS design flows, t est views, power intent .
- Provide templates for views and view generation flows that can be smoothly integrated in IP design automation flows
- Develop and deploy verification methodologies, flows , testbench and test case generation automation.
- Interact closely with EDA vendors of tools and flows in, RTL simulation and analysis, Logic equivalence checking, power intent checking, test generation and test analysis, RTL synthesis.
- Us e scripting languages in a UNIX environment as well as advanced revision control and regression automation.
- Work with cross-geo, cross-functional teams to understand requirements and communicate resolution in a timely manner .
- Mentor and train junior engineers towards building effective software and automation features.
Required Qualifications :
- Expertise in methodology front-end modelling of IP design blocks with focus on foundational IP: logic, IO, and memory
- Verilog for RTL simulation
- Gate simulation and timing annotation
- Assertions
- Verification test vector generation, coverage and regression automation
- Production t est views , test vector generation, test insertion, test coverage analysis
- Modelling and verification of power intent
- Sound knowledge of industry standard EDA tools and flows to support foundational IP , standard cell and memory designs with focus on
- RTL simulation tools and flows
- RTL synthesis and implementation flows
- Logic equivalence checking
- Static and energetic assertion verification
- Static and dynamic power intent verification
Preferred Qualifications:
- Requires a Bachelor of Engineering (B.E.) or equivalent degree in a related field from an accredited university.
- B.E./ B.Tech + minimum of 10 + years of relevant industry experience