Job Description

Role Summary

Own the end-to-end PCIe system design for an NVMe SSD product line across client laptops and enterprise servers, from PHY/MAC review through ASIC/SoC integration, PCIe SFR/register analysis, and firmware design guidelines for robust link training, link transitions, low-power behavior. This role sits at the intersection of PCIe spec compliance, NVMe behavior, FW architecture, platform interoperability, and power/performance tuning.

Key Responsibilities

- Own system‑level PCIe Gen5/Gen6 architecture from an NVMe SSD endpoint perspective
- Define and review PCIe + NVMe integration across SSD products
- PHY + MAC IP review, integration requirements and constraints
- SoC/ASIC integration: clocks, resets, power domains, straps, lane mapping, sidebands
- PCIe SFR + FW guidelines: flow control, LTSSM observability, power states,



error handling
- Link & low power transitions: DLRM, L1, L1SS, L0p, ASPM, clock-down, APST Coordination
- Bring-up + debug: enumeration, speed negotiation, width detection, stability, AER/error recovery
- Customer requirement tuning: latency/power, performance, reliability and consistency
- Provide deep expertise in PCIe configuration and extended capability registers, including:
- Link, power management, MSI/MSI‑X, AER, BARs, L1SS

- Lead platform bring‑up and debug:

- Enumeration, link training, speed negotiation, power states, error handling

- Act as the technical authority for cross‑team and customer escalations

📌 Staff Memory Systems Design Engineer (Bengaluru)
🏢 Sandisk
📍 Bengaluru