RTL SoC Integration Engineer – Camera Serializer / ASA-ML (Bengaluru)

RTL SoC Integration Engineer – Camera Serializer / ASA-ML (Bengaluru)

13 Aug
|
Best NanoTech
|
Bengaluru

13 Aug

Best NanoTech

Bengaluru

RTL SoC Integration Engineer Camera Serializer / ASA-ML

Location: Bengaluru (BLR), India
Work Mode: In office
Experience Range: 5 10 years preferred
Open Positions: 5

Role Overview

We are looking for an RTL SoC Integration Engineer with strong experience in third-party IP integration, RTL design, CDC, bus/interface integration, and functional safety. The primary responsibility will be the integration of third-party ASA IP into a Camera Serializer digital subsystem, including ASA-ML PHY integration, ASEP interfaces, CSR/register architecture, and digital analog co-simulation.

The engineer will own integration activities from RTL implementation and interface adaptation through lint/CDC closure, verification support, and FuSa-related safety mechanism integration.

Key Responsibilities

- Own end-to-end third-party IP integration into the Camera Serializer digital subsystem.
- Integrate ASA-ML-T-22ULL PHY and associated digital interfaces into the SoC/subsystem architecture.
- Perform multi-clock and multi-domain CDC analysis, identify violations, and drive CDC closure.
- Design and integrate ASEP 8-port interfaces, including 32-bit to 16-bit width adaptation.
- Implement asynchronous FIFOs, stype routing, and SOP/EOP framing for data-path interfaces.
- Develop and integrate APB / SoC slave bus bridges and associated control interfaces.
- Own the register map and CSR architecture, including RGGEN-based register generation methodology.
- Develop synthesizable SystemVerilog RTL and SystemVerilog assertions for integration and interface-level checks.
- Perform RTL linting using Cadence HAL and/or Synopsys SpyGlass and drive lint violations to closure.
- Execute CDC analysis using Cadence CDC tools and resolve clock/reset domain crossing issues.
- Support digital and Analog/Mixed-Signal IP co-simulations, debugging interface and integration issues across domains.
- Integrate MBIST, LBIST, redundancy, diagnostics,



and other safety mechanisms required for chip-level Functional Safety compliance.

Required Qualifications
- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Microelectronics, Computer Engineering, or a related discipline.
- 5+ years of relevant experience in RTL Design, SoC Integration, IP Integration, or Digital IC Design.
- Hands-on experience integrating complex third-party digital and/or mixed-signal IP into SoC or subsystem designs.
- Strong understanding of clock domain crossing, reset domain crossing, asynchronous interfaces, and FIFO architectures.
- Experience with SystemVerilog RTL development and integration-level assertions.
- Good understanding of SoC register architecture and peripheral/control bus interfaces.
- Ability to interpret PHY datasheets, interface specifications, protocol specifications, and IP integration documents.
- Experience working with cross-functional RTL, verification, analog/mixed-signal, DFT, and physical design teams.

Technical Skills RTL & SoC Integration
- SystemVerilog RTL
- Third-Party IP Integration
- SoC / Subsystem Integration
- Interface Adaptation
- RTL Assertions
- Clock and Reset Architecture

ASA / Camera Serializer
- ASA-ML
- ASA-ML-T-22ULL PHY Integration
- ASEP Interface
- ASA-ML DLL
- PCS
- OAM
- PTB
- PHY specification and datasheet interpretation

Interface & Data Path
- ASEP 8-Port Interface
- 32-to-16-bit Width Adaptation
- Asynchronous FIFO Design
- Stype Routing
- SOP/EOP Framing
- APB / SoC Slave Bus Bridge

CSR / Register Architecture
- Register Map Ownership
- CSR Design and Integration
- RGGEN-Based CSR Methodology
- APB Register Interfaces

RTL Quality & CDC
- Multi-Domain CDC Analysis
- CDC Closure
- Cadence CDC Tools
- Cadence HAL
- Synopsys SpyGlass
- RTL Lint and Lint Closure

Mixed-Signal Integration
- Digital Analog/Mixed-Signal IP Integration
- Digital / AMS Co-Simulation
- Interface-Level Debugging

DFT & Functional Safety
- MBIST
- LBIST
- Redundancy Mechanisms
- Safety Mechanisms
- Functional Safety / FuSa
- Diagnostic and fault-detection concepts

#LI-SD1

📌 RTL SoC Integration Engineer – Camera Serializer / ASA-ML (Bengaluru)
🏢 Best NanoTech
📍 Bengaluru

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