Lead - RTL Design Engineer (Mumbai)

Lead - RTL Design Engineer (Mumbai)

13 Aug
|
TCS
|
Mumbai

13 Aug

TCS

Mumbai

Member Technical Staff / Principal RTL Design Engineer – 10+ YearsDefine RTL architecture and design strategy for complex SoCsOwn SoC-level integration, clocks, resets, and power intentReview and sign off RTL quality, lint/CDC, and low-power readinessDrive RTL methodologies, coding guidelines, and best practicesMentor RTL engineers and provide technical leadershipInterface with customers and cross-functional stakeholders

Tools & SkillsLanguages: Verilog, SystemVerilogChecks: Lint, CDC/RDC, LECSynthesis Awareness: Design Compiler, GenusLow Power: UPF/CPFProtocols: AMBA (AXI/AHB/APB), SPI, I2C, UART (as applicable)Scripting: Tcl, Python, Shell

📌 Lead - RTL Design Engineer (Mumbai)
🏢 TCS
📍 Mumbai

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