20 Gbps) 99% stuck-at, transition, path delay fault coverage)Develop and integrate scan insertion flows for large digital subsystems — including full-scan, partial-scan, and scan compression (X-Bounding, EDT, TK-Scan)Implement Memory Built-In Self-Test (MBIST) for embedded SRAMs, ROMs, and register files within the So CDesign and implement Logic BIST (LBIST) infrastructure for in-system and in-field diagnostic test capabilities — critical for automotive functional safety (ISO 26262)Develop ATE test programs and ATPG patterns for manufacturing test on Advantest / Teradyne platforms, optimizing for test time and coverage Implement IEEE 1687 (i JTAG) network for embedded instrument access and hierarchical test access across complex So C subsystems Collaborate with analog design teams to define testability solutions for mixed-signal blocks — including DAC/ADC test modes, PLL characterization modes, and Ser Des loopback Partner with physical design teams to ensure DFT-aware floorplanning, scan routing, and test clock tree implementation Drive DFT sign-off — validating ATPG coverage,
test pattern simulation, and correlation between simulation and ATE results✅ Required Qualifications Education: B. Tech / M. Tech in VLSI / Electronics / Computer Engineering Experience: 3–10 years of DFT engineering experience on complex digital or mixed-signal So Cs Solid expertise in scan insertion and scan compression (Synopsys DFT Compiler, Mentor DFTADVISOR, or equivalent)Proficiency in ATPG pattern generation and fault simulation (Synopsys Tetra MAX, Cadence Modus, or equivalent)Experience with MBIST implementation and verification for embedded memories Working knowledge of JTAG (IEEE 1149.1) and boundary scan methodologies Understanding of ATE test program development (Advantest 93 K, Teradyne Ultra FLEX preferred)Familiarity with automotive DFT quality standards (zero-defect, PPM targets, AEC-Q100) Preferred / Good-to-Have Skills Experience with LBIST implementation for automotive f