About the Role:

We are hiring an experienced DFT (Design-for-Test) Lead to join our growing team. The ideal candidate will have strong technical expertise in Scan, ATPG, MBIST, post-silicon bring-up, and GLS (Timing Sim), along with proven leadership experience. If you're passionate about silicon quality and test architecture, this is your opportunity to shape high-impact silicon solutions from design to production.

Key Responsibilities:
- Lead and drive DFT architecture and implementation for SoCs.
- Hands-on execution of Scan/MBIST insertion, ATPG pattern generation & verification, MBIST verification, and GLS (Gate Level Simulation).
- Post-silicon bring-up support, debug, and yield analysis.
- Define and manage test mode timing constraints, work with timing teams for timing closure.
- Coordinate tapeout readiness from DFT standpoint and ensure test quality.
- Collaborate cross-functionally with RTL, STA, and PD teams for smooth integration.




- Mentor and guide junior engineers in DFT methodologies and best practices.
- Utilize scripting languages (Perl, Shell, etc.) for automation and flow enhancements.

Requirements
Qualifications:
- B.E./B.Tech or M.E./M.Tech in Electronics/Electrical/VLSI.
- 6+ years of relevant experience in DFT.
- Strong understanding of test coverage, fault models, and DFT flow automation.
- Prior experience in tapeout, cross-domain collaboration, and team leadership is a must.
- Excellent interpersonal and communication skills.

Why Join Us?
- Work on cutting-edge SoC and semiconductor projects.
- Prospect to lead, innovate, and grow in a collaborative environment.
- Competitive salary and benefits as per industry standards.

📌 Lead Engineer (Bengaluru)
🏢 SignOff Semiconductors
📍 Bengaluru