? Hiring: Physical Design Engineer (ASIC/VLSI)

? Location: Noida

? Experience: 5 – 12 Years

? Budget: 30–40% hike on current CTC

â±ï¸ Notice Period: Immediate joiners preferred

? Role Overview

We are seeking skilled Physical Design Engineers with solid expertise in end-to-end ASIC implementation and timing closure across advanced technology nodes.

? Key Responsibilities
- Execute RTL-to-GDSII flow: Floorplanning, Placement, CTS, Routing & Signoff
- Drive timing closure and optimize PPA (Power, Performance, Area)
- Fix setup/hold violations using STA
- Ensure DRC/LVS and IR/EM clean design
- Collaborate with RTL, DFT & verification teams

â Key Requirements
- 4+ years in ASIC/VLSI Physical Design
- Hands-on experience with Cadence Innovus / Synopsys ICC2
- Strong expertise in STA using Synopsys PrimeTime
- Knowledge of Mentor Calibre (physical verification)
- Scripting skills in TCL/Shell/Python

? Why Join
- Work on cutting-edge semiconductor designs
- High-growth, performance-driven environment
- Competitive compensation

📌 Physical Design Engineer (Noida)
🏢 Vrinda International
📍 Noida