? Hiring: STA & Full Chip Design Engineer

? Location: Bangalore

? Experience: 3 – 5+ Years

? Budget: 30–40% hike on current CTC

â±ï¸ Notice Period: Immediate joiners (Join before 30th April)

? Role Overview

We are looking for STA & Full Chip Design Engineers with strong expertise in timing analysis, closure, and sign-off. Ideal candidates should be ready to contribute from day one in a fast-paced semiconductor environment.

? Key Responsibilities
- Perform Static Timing Analysis (STA) across corners/modes
- Drive timing closure and optimization
- Handle full chip timing sign-off activities
- Analyze and fix setup/hold violations
- Collaborate with PD, RTL, and verification teams

â Key Requirements
- 3–5+ years of core STA/Full Chip Design experience
- Strong expertise in timing closure & sign-off
- Experience in multi-corner multi-mode (MCMM) analysis
- Valuable understanding of ASIC design flow

? Why Join
- Work on advanced chip design projects
- High-impact role with growth opportunities
- Competitive compensation

📌 STA & Full Chip Design Engineer (Bengaluru)
🏢 Vrinda International
📍 Bengaluru