Description
This role is for one of the Weekday's clients
Salary range: Rs 700000 - Rs 2500000 (ie INR 7 - 25 LPA)
Min Experience: 3 years
Location: NCR, Bengaluru, Hyderabad
JobType: full-time
We are looking for a talented and detail-oriented DFT Engineer with 3–8 years of experience in Design-for-Test methodologies to join our semiconductor design team. The ideal candidate will play a key role in implementing and validating robust DFT architectures that ensure high manufacturing test coverage, improved product quality, and productive silicon bring-up. You will work closely with RTL designers, verification engineers, physical design teams, and test engineers throughout the ASIC/SoC development lifecycle.
This role requires strong expertise in Automatic Test Pattern Generation (ATPG) and RTL, along with a solid understanding of scan insertion, fault modeling, and testability concepts. Experience with JTAG and boundary scan implementation will be an added advantage.
Requirements
Key Responsibilities
- Develop and implement DFT architectures for complex ASIC and SoC designs.
- Perform scan insertion, scan chain stitching, compression implementation, and DFT rule checks.
- Generate and optimize test patterns using ATPG tools to achieve high fault coverage while minimizing test time.
- Analyze stuck-at, transition, bridge, and path delay faults to improve manufacturing test quality.
- Collaborate with RTL designers to integrate DFT features early in the design cycle and ensure design-for-test compliance.
- Review and debug RTL code to resolve DFT-related issues and optimize testability.
- Validate DFT implementation through simulation, verification, and silicon bring-up activities.
- Work closely with physical design teams to ensure successful scan chain implementation and timing closure.
- Support post-silicon debug, yield improvement, and failure analysis by identifying root causes and implementing corrective actions.
- Maintain DFT documentation, test plans, and im
📌 DFT Engineer (Delhi)
🏢 Weekday AI
📍 Delhi
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