About the Role
Are you passionate about building high-quality silicon and solving complex verification challenges? We are looking for an experienced Design Verification Engineer to join our growing semiconductor team. In this role, you will be responsible for validating next-generation ASIC/SoC designs, developing robust verification environments, and driving verification closure for cutting-edge products.
Key Responsibilities
Develop and execute verification plans using SystemVerilog/UVM.
Build and maintain reusable verification environments and testbenches.
Perform RTL verification using industry-standard simulation tools.
Debug verification failures and collaborate with design teams to resolve issues.
Drive functional and code coverage closure.
Participate in design reviews and verification sign-off activities.
Required Skills
5-15 years of ASIC/SoC Design Verification experience.
Strong expertise in SystemVerilog, Verilog, and UVM.
Solid understanding of digital design fundamentals.
Experience with simulators such as VCS, Xcelium/Incisive, or ModelSim.
Solid debugging, analytical, and problem-solving skills.
Good communication and teamwork abilities.
Preferred Skills
Experience with scripting languages such as Python, Perl, or Shell.
Exposure to protocols such as PCIe, DDR, Ethernet, AXI, AHB, or APB.
Why Join Us?
Work on cutting-edge semiconductor technologies.
Collaborate with industry-leading engineering teams.
Excellent learning, growth, and career development opportunities.