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* Own and drive custom analog and mixed-signal layout for critical LPDDR PHY
blocks, including Datapath, bias networks, IO front ends, and reference
circuits, ensuring robust operation across PVT, low noise coupling, and high
matching accuracy
* 3-12 years of solid hands-on experience in custom analog and high-speed
layout design, with proven expertise in implementing and delivering critical
analog blocks and LPDDR/high-speed interfaces at advanced technology nodes
* Lead high-speed LPDDR (LPDDRx) interface layout execution, solving complex
signal integrity challenges such as skew control, impedance matching,
shielding, crosstalk mitigation, and jitter sensitivity in advanced nodes
* Architect and implement scalable array-based layout strategies for DQ/DQS
byte lanes, CA lanes,



and replica paths, ensuring strict symmetry, pitch
matching, repeatability, and multi-channel scalability
* Drive integration of custom digital and mixed-signal blocks within the PHY
(training logic, calibration engines, test/debug circuitry), ensuring optimal
clocking, congestion management, and isolation from sensitive analog regions
* Lead layout-aware co-design with circuit teams, enabling early closure of
timing, noise, IR, EM, and parasitic effects, and influencing design
decisions from a layout perspective
* Establish robust power distribution, grounding, and isolation strategies,
including guard rings, deep N-well usage, decoupling, and domain separation
for high-speed and analog-sensitive regions
* Own physical verification and signoff closure:
* DRC/LVS, parasitic extraction, and simulation correlation
* Ensure silicon-accurate performance for analog-intensive and high-speed
LPDDR blo

📌 Senior /Staff AMS Layout engineer-DPG-LPDDR (Hyderabad)
🏢 Micron Technology
📍 Hyderabad