Our vision is to transform how the world uses information to enrich life for
all.
Micron Technology is a world leader in innovating memory and storage solutions
that accelerate the transformation of information into intelligence, inspiring
the world to learn, communicate and advance faster than ever.
As a Senior Memory Layout Engineer-DPG-LPDDR at Micron, you will work on
innovative memory and storage solutions. These solutions help transform data
into intelligence quickly. You will join a dedicated team collaborating to
develop world-class products that set industry standards.
* Hands-on experience on Bit cell layout creation and pitch matching
* Strong exposure on Row decoder (XDEC) and column decoder (YDEC) layout
development
* 2+ years of proven experience in memory and full-custom layout development
* Memory array hierarchy and decode path understanding
* Proficient with Cadence Virtuoso for custom layout implementation
* Solid experience with Calibre DRC/LVS including debug and closure
* Strong understanding of DRAM/LPDDR memory architecture, array organization,
and peripheral integration
* Apply robust device physics expertise to drive high‑quality layout
implementation, including transistor matching strategies, well and substrate
engineering, parasitic optimization, and EM/ESD reliability considerations.
* Ability to independently plan, execute and deliver layout blocks with minimal
supervision
* Strong ownership mindset with focus on quality, power and schedule
* Leverage AI/ML knowledge as a value-add to support data-driven optimization,
layout automation initiatives, and improved debug and correlation workflows.
* Leveraging Artificial Intelligence
Education
* B. Tech/B. E in Electronics, Electronics & Communications, or VLSI
Engineering
* M. Tech in Electronics engineering, Microelectronics or VLSI Engineering
About Micron Technology, Inc.
We are an industry leader in innovative memory and storage solutions
transforming how the world uses informat