About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As a key CAD member of Marvell Central Engineering, you will play a leading role on developing next-generation automated design flow and its add-on tools. You will have the opportunity to use your extensive design and CAD knowledge to participate in defining the whole organization's design infrastructure, methodology and workflows.
What You Can Expect
Develop, maintain, and enhance PrimeTime-STA & PrimePower-based power signoff flows within Marvell's M1DP CAD platform.
Solid understanding of STA flows including dealing with hierarchical designs
Understanding of using Hyperscale & Context models for Hierarchical STA analysis
Solid understanding of power estimation flows (average and time-based)
Enable and support In-Design Timing & Power flows for timing/power-aware optimization during physical implementation.
Collaborate with Physical Design and Front-End teams to set up FSDB/activity files, UPF/CLP power intent, and SAIF/vector annotation for accurate power computation.
Develop and maintain glitch analysis and optimization flows, including configuration of glitch-aware datapath optimization settings is a plus
Generate, validate, and deliver power analysis reports (energetic, leakage, glitch) to design teams across multiple ASIC projects by building power dashboard
Experience with PrimePower RTL 2.0 adoption for early-stage power estimation, enabling designers to identify and resolve power issues be