The Role and Impact: As a Physical Design Timing Engineer, you will play a
pivotal role in advancing Intel's next-generation SoCs by ensuring their optimal
performance and efficiency. Your expertise will directly impact the success of
Intel's products, enabling innovation across high-performance computing, AI, and
beyond. You will work on cutting-edge designs, collaborating with
cross-functional teams to tackle complex challenges while delivering
high-quality timing models that empower the physical design team to excel. This
is an exciting chance to contribute to Intel's mission of shaping the
future of technology. Key Responsibilities: - Perform timing analysis and
optimization to ensure design functionality and performance at the chip and
block levels. - Generate and verify timing constraints, addressing and resolving
timing violations during SoC development. - Conduct timing rollups, develop and
implement power-optimized clock networks, and ensure alignment with
high-performance, low-power guidelines. - Define and implement methodologies to
deliver quality timing models that enhance the efficiency of the physical design
process. - Set process, voltage, and temperature (PVT) conditions for timing
analysis based on product plans and operating conditions. - Collaborate with
architecture, clock design, logic design, and backend teams to achieve clocking
balance, power delivery optimization, and efficient partitioning. - Partner
closely with the clocking team to refine methodologies and validate integration
flows for chip-level timing solutions.
QUALIFICATIONS:
Minimum Qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a
related field.
- 8+ years of experience in Physical Design with a Bachelor's degree, 6+ years
with a Master's degree, or 4+ years with a PhD.
- Proficiency in static timing analysis tools and methodologies.
- Demonstrated expertise in timing modeling, verification, constraint