About the Role

We are seeking a highly motivated Physical Design (PD) Engineer with strong expertise in full-chip implementation flows from Netlist to GDS-II. The ideal candidate will have hands-on experience in advanced technology nodes (22nm, 12nm and below preferred) and deep knowledge of PnR, STA, and signoff methodologies.

In this role, you will take ownership of end-to-end physical implementation, ensuring high-performance, low-power, and timing-closed designs while meeting stringent quality and signoff requirements

Key Responsibilities
- Execute full-chip Place and Route (PnR) from Netlist to GDS-II.
- Perform floor-planning, placement, CTS, routing, and timing closure (STA).
- Drive block-level and full-chip timing signoff, including ECO generation.
- Handle physical synthesis through signoff GDS-II generation.
- Ensure convergence of timing, power, and physical signoff metrics.
- Perform and manage signoff checks: PV, EMIR & VCLP




- Work with industry-standard tools such as: Fusion Compiler/Innovus
- Develop and maintain Tcl scripts for automation and flow improvements.
- Collaborate with RTL, synthesis, DFT, and verification teams for seamless execution.

Required Qualifications
- Bachelors or Masters degree in Electrical, Electronics, or Computer Engineering.
- 3-7 years of hands-on experience in Physical design.
- Solid expertise in: Full-chip PnR, Floor-planning, CTS, Routing, Static Timing Analysis (STA) and timing closure, Signoff flows (PV, VCLP & EMIR) & Physical synthesis to GDS-II
- Experience in scripting (Tcl, Perl, Python) for automation and analysis.
- Excellent problem-solving skills and ability to work independently in fast-paced environments.

To apply, please send your resume (PDF format ) to [email protected]

📌 Physical Design Engineer (Bengaluru)
🏢 SVTek
📍 Bengaluru