Lattice Semiconductor is seeking a SoC RTL Design Engineer to join the HW design team focused on IP design and full chip integration. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow.
Role specifics:
- This is a full-time individual contributor position located in Pune, India.
- The role will focus on FPGA projects concentrated in Pune and similar time zones.
- The qualified candidate will be working in RTL design, best-in-class coding styles, algorithms, and both Verilog and System Verilog.
- The qualified candidate will be working in SoC integration and associated quality checks including lint, CDC, RDC, SDC etc.
- The role requires to work with architect and micro-architect team to understand define design specifications
- The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics.
This role carries the need to be both a robust educator and an open-minded student.
Accountabilities:
- Serve as a key contributor to FPGA design efforts.
- Drive logic design of key FPGA blocks full chip and bring best-in-class methodologies to accelerate design time and improve design quality.
- Ensuring design quality through assertions, checkers, and scripting.
- Develop strong relationships with worldwide teams.
- Mentor and develop strong partners and colleagues.
- Occasional travel as needed.
Required Skills:
- BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent.
- 6+ years of experience in driving logic design across a multitude of silicon projects.
- Expertise in SoC integration, defining micro-architecture and experience of selecting 3rd party IP.
- Experience in working with ARM processor, AXI, AMBA bus, ENET, PCIE, safety and security protocols, debug architecture will be plus.
- Familiarity with FPGA de