Job Responsibilities
- Develop and implement DFT architecture for complex SoC/ASIC designs.
- Insert and verify DFT logic including Scan, MBIST, Boundary Scan (JTAG), and Compression.
- Generate ATPG patterns and perform fault coverage analysis.
- Debug DFT and ATPG issues during simulation and silicon bring-up.
- Collaborate with RTL, Physical Design, and Verification teams for DFT implementation and sign-off.
- Perform DFT validation using industry-standard EDA tools.
Required Skills
- 4+ years of hands-on experience in ASIC DFT.
- Solid expertise in Scan Insertion, Scan Compression, MBIST, LBIST (preferred),
JTAG/IEEE 1149.1.
- Experience with ATPG, fault simulation, and coverage analysis.
- Hands-on experience with
Siemens Tessent
suite (Scan, MBIST, ATPG) or equivalent DFT tools.
- Good understanding of ASIC design flow, RTL, and synthesis.
- Knowledge of Verilog/SystemVerilog and scripting using Tcl/Perl/Python.
- Familiarity with STA, CDC, and low-power concepts is an added advantage.
Preferred:
Experience in advanced technology nodes and successful silicon bring-up.