Marvell s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
Your Team, Your Impact
Marvell Data Centre Engineering (DCE) - Compute Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast growing product lines, Marvell Technology is powering the next generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions Enterprise/Career solutions including the CXL product line
What You Can Expect
- Own and drive PCIe/CXL subsystem micro architecture definition , RTL implementation, and integration
- Collaborate closely with Architecture teams to translate requirements into robust RTL designs
- Work with Design Verification teams on test plan reviews, debug, and coverage closure
- Partner with Physical Design and DFT teams to ensure PD friendly and DFT ready RTL
- Support silicon bring up and post silicon debug , working with firmware and validation teams
- Drive design quality improvements, coding best practices, and reuse across projects
- Participate in design reviews, milestone reviews, and cross functional technical discussions
- Mentor junior designers and provide technical leadership within the PCIe/CXL design domain
What Were Looking For
- Master s/Bachelor s degree in Electronics/electrical Engineering with 8+ years of relevant experience in RTL design
- Experience on end to end PCIe/CXL subsystem RTL design execution and sign off
- Proven experience delivering complex PCIe/CXL IP or subsystems from architecture through RTL closure
- Solid hands on experience in SystemVerilog /