K
ey Responsibilities
- Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
- Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
- Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
- Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
- Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
- Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
- Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
- Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
- Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
- Experience with MBIST implementation and verification; SMS experience preferred.

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📌 DFT Engineer (Bangalore Metropolitan Area)
🏢 Hepl
📍 Bangalore Metropolitan Area