The focus of this role in the AECG ASIC organization is to lead design verification for next generation ASICs that meet Engineering, Business and Customer requirements.
THE PERSON:
You have a passion to lead high performance ASIC verification and emulation teams. You are a team player who has excellent communication skills and experience collaborating in a corporate environment with other architects engineers located in different sites/time-zones. You have robust analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- SoC RTL Integration for complex digital blocks and ASIC top level to ensure high quality
- Verifying RTL implementation for complex digital blocks and ASIC top level to ensure high quality
- Develop design and verification strategies for new features, plan volume validation and coverage strategies
- Writing testplan, developing testbenches,
coding test/sequences and checker to support IP level verification in constrained-random and/or directed verification environments using System Verilog UVM
- Drive coverage analysis and take necessary actions to meet coverage goals
- Integrate VIPs as needed
- Closely work with design teams to drive feature enablement
- Lead internal and external teams
PREFERRED EXPERIENCE:
- Strong foundation in SoC architecture and processor systems with proven years of experience
- Good analytical problem solving, and attention to details
- Working knowledge of C, SystemC, and Python
- Excellent written and verbal communication skills
- Knowledge of CPU, AXI Interconnect, and I/O peripherals
- Knowledge of SOC development flow and accelerator IP
- Experience in micro-architecture and digital design/verification
- Knowledge of power management, boot, security and RAS architectures
- Exposure to performance modeling and analysis
- Expert experience with implementation of UVM/OVM and/or Verilog, System Verilog test benches and/o