Our vision is to transform how the world uses information to enrich life for *all*.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Job Description

Role and Responsibilities
- Own the development and physical implementation of critical analog, mixed‑signal, and custom digital blocks, including block‑level and full‑chip layout ownership.
- Lead layout implementation using AI‑assisted and automated workflows, applying copilot‑based assistants, agentic AI flows, and rule‑aware automation to accelerate placement, routing and optimization.
- Perform and automate layout verification activities, including DRC, LVS, Antenna, Yield, ESD, TOTEM, EM/IR and quality checks.
- Drive on‑time delivery of blocks and partition‑level layouts with predictable quality and risk prediction/mitigation plans.
- Develop and deploy AI‑enabled methodologies for Semi-automated floorplanning, parasitic estimation,



layout consistency checks and best‑practice enforcement, repetitive layout task elimination via SKILL, Python, TCL or agent‑based flows.
- Demonstrate technical leadership in planning, area and cycle‑time estimation, delegation and execution.
- Guide and mentor engineers in Analog layout fundamentals, Automation‑first approach, Design‑for‑quality and design‑for‑yield practices
- Collaborate closely with Design, CAD, Verification, Reliability, and Program Management teams, clearly communicating technical risks, schedule impacts and any optimization opportunities.
- Drive continuous improvement by identifying manual bottlenecks and converting them into scalable automated flows.

Job Requirements
- 6+ years of experience in analog/custom layout design in advanced CMOS technology nodes.
- Robust expertise in Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, with hands‑on ownership of verification closure.
- Proven exper

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